Alma Samuel Babbitt
Computer systems engineering
Hometown: Mesa, Arizona, United States
Graduation date: Fall 2024
FURI | Spring 2024
Verification Code Generation in the Hardware Description Language Verilog
The hardware industry employs Verilog and other hardware description languages to design and test a variety of application-specific integrated circuits. The process of verifying a circuit design is non-trivial and requires many resources to ensure functionality. This study attempts to create a machine learning model that generates verification code given a circuit design and its specification document. This tool for verification code generation in Verilog intends to shorten the testing phase of the design process and remove roadblocks engineers face when designing chips. Future work would be to create a larger training data set that incorporates visual abstractions and waveforms.
Mentor: Nakul Gopalan
It’s hip to be square.
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Sponsored project | Spring 2024
Alma Babbitt’s FURI project is sponsored by TSMC.
TSMC is a global leader in the semiconductor foundry business. The company’s industry-leading process technologies and portfolio of design enablement solutions help its customers and partners unleash semiconductor innovation. With its recent expansion into Phoenix, TSMC sees the benefit of a strong partnership with ASU faculty and student researchers. TSMC supports the FURI program by providing additional funding for exceptional research projects related to the semiconductor industry. FURI student researchers who pursue a project related to the Semiconductor Manufacturing research theme are eligible for this sponsorship. TSMC-supported FURI students receive a $2,600 stipend and $400 to use for materials. Exceptional research proposals that align with the research theme of Semiconductor Manufacturing will be considered for this additional funding.